1. Field of Invention
The present invention relates to an integrated circuit. More particularly, the present invention relates to a duty cycle corrector with a single gate duty adjuster.
2. Description of Related Art
In recent years, the performance demands for consumer electronic products, such as mobile phones and tablets, are increasing, thus resulting in the need of increasing clock speed and accurate signal timings for a proper operation. For example, the speed of data access in these consumer electronic products has been a bottleneck in recent years. Although a dynamic random access memory (DRAM) has been developed to provide faster access time with a scaled down manufacturing process, the DRAM faces extreme challenges in reliability.
For example, a challenge of generating the accurate clock signals is to generate internal clock signals while the duty cycle of the external clock signals is maintained. The duty cycle of an internal clock signal becomes distorted when the ratio of high voltage level to low voltage level of an internal clock signal is different from the ratio of high voltage level to low voltage level of the external clock signals.
The manufacturing process distorts the duty cycle. In other words, the clock generation circuits are distorted by the variation of the manufacturing process. As a result, the duty cycle distortion may reduce the performance of DRAM. Further, in certain cases, the duty cycle distortion may cause a failure in DRAM.
Therefore, a heretofore unaddressed need exists for correcting the system clock signals to address the aforementioned deficiencies and inadequacies.